/************************
*
*
*
*
*************************/


#ifndef __HS6200_H_
#define __HS6200_H_

//------Hardware SPI define ----
//The next is need modify if new hardware fram
//#define	__HS6200_HARDWARE_SPI
#define	__HS6200_USE_CE_CTRL

#ifdef		__HS6200_USE_CE_CTRL
sbit HS6200_CE = P0^0;  
sbit HS6200_IRQ = P0^6;

#define	HS6200_CE_HIGH		HS6200_CE = 1	
#define	HS6200_CE_LOW		HS6200_CE = 0		
#endif

#define	HS6200_CSN_HIGH		NSSMD0 = 0x01 
#define	HS6200_CSN_LOW		NSSMD0 = 0x00  

//SPI_Flag
#define SPI_FLG_BUSY       0x01
#define SPI_FLG_IDLE       0x02
extern unsigned char SPI_Flag;


//-----------------RF command---------------------
#define HS6200_RD_REG					0x00 // Define read command to register
#define HS6200_WR_REG					0x20 // Define write command to register
#define HS6200_R_RX_PAYLOAD				0x61 // Define RX payload register address
#define HS6200_W_TX_PAYLOAD				0xA0 // Define TX payload register address
#define HS6200_FLUSH_TX					0xE1 // Define flush TX register command
#define HS6200_FLUSH_RX					0xE2 // Define flush RX register command
#define HS6200_REUSE_TX_PL				0xE3 // Define reuse TX payload register command
#define HS6200_ACTIVATE					0x50 // Define ACTIVATE features register command   
#define HS6200_R_RX_PL_WID				0x60 // Define read RX payload width register command
#define HS6200_W_ACK_PAYLOAD			0xA8 // Define write ACK payload register command
#define HS6200_W_TX_PAYLOAD_NOACK		0xB0 // Define disable TX ACK for one time register command
#define HS6200_NOP						0xFF // Define No Operation, might be used to read status register
#define HS6200_READ_STATUS				0xFF
#define HS6200_ACTIVATE_DATA			0x53


//----------------------defines--------------------------
#define HS6200_BANK1					0x80
#define HS6200_BANK0					0x00

//HS6200 Bank0 Register Addr
/**************************************************/               
#define HS6200_BANK0_CONFIG				0x00 // 'Config' register address
#define HS6200_BANK0_EN_AA				0x01 // 'Enable Auto Acknowledgment' register address
#define HS6200_BANK0_EN_RXADDR			0x02 // 'Enabled RX addresses' register address
#define HS6200_BANK0_SETUP_AW			0x03 // 'Setup address width' register address
#define HS6200_BANK0_SETUP_RETR			0x04 // 'Setup Auto. Retrans' register address
#define HS6200_BANK0_RF_CH				0x05 // 'RF channel' register address
#define HS6200_BANK0_RF_SETUP			0x06 // 'RF setup' register address
#define HS6200_BANK0_STATUS				0x07 // 'Status' register address
#define HS6200_BANK0_OBSERVE_TX			0x08 // 'Observe TX' register address
#define HS6200_BANK0_RPD				0x09 // 'Received Power Detector' register address
#define HS6200_BANK0_RX_ADDR_P0			0x0A // 'RX address pipe0' register address
#define HS6200_BANK0_RX_ADDR_P1			0x0B // 'RX address pipe1' register address
#define HS6200_BANK0_RX_ADDR_P2			0x0C // 'RX address pipe2' register address
#define HS6200_BANK0_RX_ADDR_P3			0x0D // 'RX address pipe3' register address
#define HS6200_BANK0_RX_ADDR_P4			0x0E // 'RX address pipe4' register address
#define HS6200_BANK0_RX_ADDR_P5			0x0F // 'RX address pipe5' register address
#define HS6200_BANK0_TX_ADDR			0x10 // 'TX address' register address
#define HS6200_BANK0_RX_PW_P0			0x11 // 'RX payload width, pipe0' register address
#define HS6200_BANK0_RX_PW_P1			0x12 // 'RX payload width, pipe1' register address
#define HS6200_BANK0_RX_PW_P2			0x13 // 'RX payload width, pipe2' register address
#define HS6200_BANK0_RX_PW_P3			0x14 // 'RX payload width, pipe3' register address
#define HS6200_BANK0_RX_PW_P4			0x15 // 'RX payload width, pipe4' register address
#define HS6200_BANK0_RX_PW_P5			0x16 // 'RX payload width, pipe5' register address
#define HS6200_BANK0_FIFO_STATUS		0x17 // 'FIFO Status Register' register address
#define HS6200_BANK0_DYNPD				0x1C // 'Enable dynamic payload length' register address
#define HS6200_BANK0_FEATURE			0x1D // 'Feature' register address
#define HS6200_BANK0_SETUP_VALUE		0x1E
#define HS6200_BANK0_PRE_GURD			0x1F


//HS6200 Bank1 register
/**************************************************/
#define HS6200_BANK1_LINE				0x00
#define HS6200_BANK1_PLL_CTL0			0x01
#define HS6200_BANK1_PLL_CTL1			0x02
#define HS6200_BANK1_CAL_CTL			0x03
#define HS6200_BANK1_A_CNT_REG			0x04
#define HS6200_BANK1_B_CNT_REG			0x05				
#define HS6200_BANK1_STATUS				0x07				
#define HS6200_BANK1_STATE				0x08				
#define HS6200_BANK1_CHAN				0x09				
#define HS6200_BANK1_IF_FREQ			0x0A				
#define HS6200_BANK1_AFC_COR			0x0B				
#define HS6200_BANK1_FDEV				0x0C				
#define HS6200_BANK1_DAC_RANGE			0x0D				
#define HS6200_BANK1_DAC_IN				0x0E				
#define HS6200_BANK1_CTUNING			0x0F				
#define HS6200_BANK1_FTUNING			0x10				
#define HS6200_BANK1_RX_CTRL			0x11				
#define HS6200_BANK1_FAGC_CTRL			0x12				
#define HS6200_BANK1_FAGC_CTRL_1		0x13				
#define HS6200_BANK1_DAC_CAL_LOW		0x17				
#define HS6200_BANK1_DAC_CAL_HI			0x18				
#define HS6200_BANK1_DOC_DACI			0x1A				
#define HS6200_BANK1_DOC_DACQ			0x1B				
#define HS6200_BANK1_AGC_CTRL			0x1C				
#define HS6200_BANK1_AGC_GAIN			0x1D				
#define HS6200_BANK1_RF_IVGEN			0x1E				
#define HS6200_BANK1_TEST_PKDET			0x1F	

/*register bit Mask define*/
/*R 0x17:*/
#define HS6200_FIFO_STA_TX_REUSE		0x40
#define HS6200_FIFO_STA_TX_FULL			0x20
#define HS6200_FIFO_STA_TX_EMPTY		0x10
#define HS6200_FIFO_STA_RX_FULL			0x02
#define HS6200_FIFO_STA_RX_EMPTY		0x01
/*R 0x07*/
#define HS6200_STATUS_RX_DR				0x40
#define HS6200_STATUS_TX_DS				0x20
#define HS6200_STATUS_MAX_RT			0x10
#define HS6200_STATUS_TX_FULL			0x01

/*pramr define*/
#define HS6200_FIFO_MAX_PACK_SIZE		0x20

typedef enum {
	Rf_PRX_Mode = 0,
	Rf_PTX_Mode,
	Rf_Carrier_Mode
}HS6200_ModeTypeDef;

typedef enum {
	HS6200_Bank0 = 0,
	HS6200_Bank1
}HS6200_Bank_TypeDef;


/*************************************************
	hardware & interface function define
**************************************************/

/*SPI driver*/
unsigned char HS6200_spi_wrd(unsigned char Data);
/*Write One Register*/
void HS6200_write_byte(unsigned char addr,unsigned char D);
/*Read One Register */
unsigned char HS6200_read_byte(unsigned char addr);
/*Write a buffer into continue addresses*/
void HS6200_wr_buffer(unsigned char addr,unsigned char* buf,unsigned char len);
/*read continue addresses out to  a buffer*/
void HS6200_read_buffer(unsigned char addr,unsigned char* buf,unsigned char len);


/*************************************************
				Base function define
**************************************************/

/*write Commad	function, cmd = code; D = data*/
void HS6200_wr_cmd(unsigned char cmd,unsigned char D);
/*Operation Commad  function*/
unsigned char HS6200_Operation(unsigned char opt);


/**************************************************
			Rf module funtion define
***************************************************/

/* Switch register Bank*/
void HS6200_bank_Switch(HS6200_Bank_TypeDef bank);
/* set CE high*/
void HS6200_CE_High(void);
/* set CE low*/
void HS6200_CE_Low(void);
/*Read_Status*/
unsigned char HS6200_Read_Status(void);
/*change the tx and rx addr*/
void HS6200_ChangeAddr_Reg(unsigned char* AddrBuf,unsigned char len);
/*Configuration Reg*/
void HS6200_Configuration_Reg(unsigned char* Dbuf,unsigned char* Cbuf,unsigned char len);
/*change the channel*/
void HS6200_Change_CH(unsigned char ch_index);
/*get chip id*/
unsigned char HS6200_Get_Chip_ID(void);
/*Mode_Switch*/						 
void HS6200_ModeSwitch(HS6200_ModeTypeDef mod);
/*buf:data buffer; len:[1~32] ; cmd: HS6200_W_TX_PAYLOAD/HS6200_W_TX_PAYLOAD_NOACK*/
void HS6200_SendPack(unsigned char cmd, unsigned char* buf, unsigned char len);
/*buf:data read from rx buffer*/
unsigned char HS6200_RecivePack(unsigned char* buf);
/*set Auto_ACK msg*/
void HS6200_Write_Ack_Payload(unsigned char PipeNum, unsigned char *pBuf, unsigned char bytes);
/*Clear All Irq*/
void HS6200_Clear_All_Irq(void);
/*Flush Tx*/
void HS6200_Flush_Tx(void);
/*Flush Rx*/
void HS6200_Flush_Rx(void);
/*init HS6200*/
void HS6200_Init(void);



#endif


